Eclipse News Desk
Start-up Claims To Crack Multicore Scaling Dilemma
He solved logic emulation by combining hundreds of FPGAs using a mesh interconnect and a patented 'virtual wires' compiler
Aug. 27, 2007 12:15 PM
Tilera Corporation, a venture-backed MIT spinout that's been operating in stealth mode for the last three years, has produced a 64-core chip that promises to flower into a family of general-purpose commercial processors that can scale to hundreds, even thousands of cores.
The chip, called the Tile64, is based on the kind of architecture that Intel has been researching but so far Intel has only publicly described an 80-tile prototype - part of its huge Tera-scale Research Project in search of teraflops chips - that has left Intel grasping for how the dickens it's going to teach programmers to write code for such a thing once it becomes a reality.
Tilera's principal founder and CTO Anant Agarwal, who's been wrestling with multiprocessors for over 15 years, says that each of his cores, each of them a standalone processor, can run 2.6 Linux and support a standard SMP Linux programming environment.
Developers simply write in garden-variety ANSI standard C, use the Eclipse IDE and the widget will run off-the-shelf applications. Tilera has dubbed it "gentle slope programming." The company's Multicore Development Environment offers both Linux and Windows hosting environments.
The chip reportedly delivers 10 times the performance and 30 times the performance-per-watt of Intel's dual-core Xeon running real-world applications and 40 times the performance of TI's DSP.
It's good, Tilera says, for 500 billion operations per second (BOPS).
The start-up brags that that it is the "first significant new chip architectural development in a decade" and thinks it could be the blueprint for all future chips.
Agarwal calls it "the Internet on a chip."
He says existing multi-core technologies won't scale beyond a handful of cores, their tools are primitive because they're based on single-core models and they eat electricity. Agarwal claims 1,000-core Tilera processors will be in common use by 2014.
Meanwhile, over at AMD, the all-important Barcelona quad is three quarters late because it was harder to pull off than they thought.
The first of the Tilera widgets, reckoned by its designers to be the world's highest-performance embedded processor, was described Monday at the Hot Chips conference at Stanford University.
Tilera calls it an embedded processor because that's the direction it's pushing it, but there's no reason on God's green earth why it couldn't be used in high-end server. And the Tile64 can be clustered and run multiple operating system instances simultaneously.
Tilera already has 10 customers including what it says are major accounts that are integrating the Tile64 into advanced networking and digital multimedia products. The company expects to deliver production parts to them in Q4 in three different frequencies and I/O capabilities at prices starting at $435 apiece for 10,000 units.
We can, it seems, expect security appliances, switches, routers, video conferencing gadgets, cable and broadcast set-tops and surveillance DVRs based on the chip.
The company's roadmap also includes plans for a low-performance 36-core due out the first half of next year and a 120-core device due in late '08-early '09.
Tilera's architecture eliminates the on-chip bus interconnect, which it consigns to the dustbin as a traffic bottleneck particularly in multi-core chips.
The company says it's why they can't scale beyond four or eight cores. See, in other people's architectures packets from the cores all have to travel to a central point like a spoke-and-wheel intersection.
(Mind you, Sun has its eight-core T1 and new T2 with the T2 aimed at the embedded market and has promised the 16-core Rock next year.)
Anyway, Tilera replaces the bus with a communications switch on each core and then lays them out in a grid on the chip, an architectural pattern it called iMesh, short for Intelligent Mesh. There are no North or South Bridges.
Coupled with some patented mojo, the layout creates an aggregate bandwidth that is orders of magnitude greater than a bus - and the distance between cores shorter, the short hops making it more energy efficient than the bus' long wires.
Tilera claims the design creates "computing-by-the-yard" scalability.
The Tile64, which includes 5MB of on-chip L1 and L2 cache, will clock in at 600MHz-1GHz and run on 170 mW to 300 mW per tile. In light bulb language that's 20 Watts total, baby, to the 97 Watts Intel is getting with 80-core prototype and Tilera's idle tiles can be put in sleep mode.
A TileExpress Appliance card or development platform is available with 12 gigE ports.
Tilera has collected 64 people from places like AMD, Intel, Broadcom, DEC, Stargen, Sun, Cisco, HP, Microsoft, Thinking Machines and Curl but they're standing on the shoulders of Agarwahl, who was involved in the first Mips Computer demonstration at Stanford back in '83 and then graduated to the 1991 development of Sparcle, an early multithreaded Sparc microprocessor created by MIT, LSI and Sun.
In 1994, his team at MIT demonstrated a 32-node mesh-based cache-coherent multiprocessor. In 1995 he started Virtual Machines, now part of Mentor Graphics, which solved logic emulation by combining hundreds of FPGAs using a mesh interconnect and a patented "virtual wires" compiler. In 2002 DARPA and the National Science Foundation funded the research that led to Tilera being set up in 2004.
Tilera has filed for 40 some odd patents.
It is funded by Bessemer Venture Partners, Walden International, Columbia Capital and VentureTech Alliance, which explains why it's using Taiwan Semiconductor Manufacturing (TSMC) as its fab, VentureTech being TSMC's investment arm. So far it's gotten $40 million in two rounds and expects to start collecting revenues soon.
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